A Digitally-enhanced Delta-sigma Fractional-N Synthesizer

Recent advances in frequency synthesizer architectures have formed the groundwork for a very exciting and active area of research. On the one hand, the need for a wider-bandwidth fractional-N synthesizer has inspired researchers to develop phase noise cancellation techniques to avoid tradeoffs between noise performance and synthesizer bandwidth [1], as shown in Figure 1. On the other hand, the continuing development of the deep submicron CMOS process has initiated people’s interest in alldigital phase locked loop (PLL) [2], which not only leverages the high-speed digital capability available in a deep submicron process but also avoids the problems those a conventional charge-pump PLL may encounter, such as high variation and leakage current. The work in [2] demonstrated that an all-digital synthesizer can meet GSM specifications, but the need of a strong DSP capability and a complicated VCO structure prevents it from being a simple solution for many applications. In addition, the bandwidth of [2] is ten times lower than that achievable by analog techniques [1]. Therefore, the goal of this research is to find a digital synthesizer solution that not only is simpler than [2] but also can achieve a high bandwidth comparable to the analog approach [1].